1. Field of the Invention
The present invention relates to a computer system having a PCI/AGP bus, and more particularly, to a video controller for automatically changing a memory clock frequency according to the number of memory control commands per unit time.
2. Description of the Related Art
In a video controller of a typical computer system, a video memory stores image data to be transmitted to a monitor. A bus interface receives transmitted commands, e.g., a control signal, data or an address signal of a central processing unit (CPU), through a host bus, and transmits the received commands to a sequential controller. The sequential controller generates an address, data and a control signal for controlling read and write with respect to the video memory to transmit the generated address, data and control signal to the video memory The control signal includes a column address strobe (CAS), a row address strobe (RAS), a write enable (WE) and an output enable (OE). A frequency synthesizer generates clock signals including a memory clock and a pixel clock. A BIOS ROM includes a BIOS code for controlling all devices, where the code is read during initializing of the device.
The CPU must periodically read a video memory to refresh a screen of the monitor, and the system performance speed deteriorates when data transmission to the video memory from the CPU increases. However, a memory clock used for controlling timing of the memory is once programmed by a bios during initializing of a video controller chip. Thus, even though the number of CPU commands is increases or decreases, the clock frequency is not changed, so that the frequency of the memory clock is constant without change regardless of a load level concerning transmission of data from the CPU to the video memory.
In the above-described memory controller, the frequency of the memory clock is set to a maximum operating frequency for a system. However, during the use of the computer, data is not always transmitted from the CPU to the memory, thereby causing a high power consumption and the generation of EMI due to the use of a high-frequency signal.
The following patents each discloses features in common with the present invention: U.S. Pat. No. 4,893,271 to Davis et al., entitled Synthesized Clock Microcomputer With Power Saving, U.S. Pat. No. 5,615,376 to Ranganathan, entitled Clock Management For Power Reduction In A Video Display Sub-System, U.S. Pat. No. 5,774,704 to Williams, entitled Apparatus And Method For Dynamic Central Processing Unit Clock Adjustment, U.S. Pat. No. 5,781,768 to Jones Jr., entitled Graphics Controller Utilizing A Variable Frequency Clock, U.S. Pat. No. 5,524,249 to Suboh, entitled Video Subsystem Power Management Apparatus And Method, U.S. Pat. No. 5,623,647 to Maitra, entitled Application Specific Clock Throttling, U.S. Pat. No. 5,619,707 to Suboh, entitled Video Subsystem Power Management Apparatus And Method, U.S. Pat. No. 5,758,133 to Evoy, entitled System And Method For Altering Bus Speed Based On Bus Utilization, U.S. Pat. No. 5,392,435 to Masui et al., entitled Microcomputer Having A System Clock Frequency That Varies In Dependence On The Number Of Nested And Held Interrupts, and U.S. Pat. No. 5,771,373 to Kau et al., entitled Power Management Masked Clock Circuitry, Systems And Methods.